The 136 Channel Logic Analysis System Frame has a state analysis speed of 100MHz.
Setup/Hold time is 0/4.5ns to 4.5/0ns adjustable in 500ps increments.
Multi window interface
Max State Clock 100MHz
On chip emulation link debugged
Multiple time correlated views
Number of channels: 136ch
Input impedance: 100Kohms
Input capacitance: 8pF
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